(a) Field of the Invention
The present invention relates to a semiconductor device including a stacked capacitor and a method for fabricating the same and, more particularly, to a semiconductor device including a stacked capacitor having an increased capacitance and a method for manufacturing such a semiconductor device.
(b) Description of the Related Art
Semiconductor devices, such as DRAM (Dynamic Random Access Memory) devices, include a plurality of memory cells having therein stacked capacitors for storing information. In the stacked capacitors, the electric charge stored therein is reduced along with the elapsed time length, and thus it is necessary to update the information stored therein by the same information at a regular interval. In this update, it is advantageous for the DRAM devices to include stacked capacitors having a larger capacitance because the larger capacitance prolongs the interval of the update and thus reduces the power dissipation of the DRAM devices. The stacked capacitor in general has a MIS structure including a silicon bottom electrode, a capacitor insulation film and a metallic top electrode, and this type of the stacked capacitor is generally called MIS capacitor.
Along with the recent higher integration density of the semiconductor elements, the space for each stacked capacitor is markedly reduced, and it becomes more and more difficult to secure the desired capacitance for the stacked capacitor. Techniques for achieving a higher capacitance with a reduced occupied area of the MIS capacitor include use of a HSG (Hemispherical Grain) structure, wherein the silicon bottom electrode has a large number of hemispherical grains on the surface thereof to have an increased surface area.
FIG. 3 shows a MIS capacitor formed in a conventional semiconductor device, such as DRAM device, and having a HSG structure on the bottom electrode thereof. In FIG. 3, the semiconductor device 30 includes a silicon substrate 11 on which an isolation film 12 made of silicon oxide is formed to isolate element-forming regions. In each of the element-forming regions, transistors each including a gate electrode (not shown) and source/drain diffused regions 13 are formed on the silicon substrate 11. On the gate electrode and the source/drain regions 13, an interlevel dielectric film 15 made of silicon oxide and another interlevel dielectric film 16 made of silicon nitride are consecutively formed.
Contact holes 14a penetrate interlevel dielectric films 15, 16 to reach the source/drain regions 13, and are filled with respective contact electrodes 14.
Another interlevel dielectric film 17 made of silicon oxide having a larger thickness is formed on interlevel dielectric film 16 and the contact electrodes 14. Capacitor-receiving holes (capacitor holes) 18 penetrate interlevel dielectric film 17 to expose respective contact electrodes 14 and a portion of interlevel dielectric film 16 in the vicinity of the contact electrodes 14. The capacitor holes 18 each receive therein a silicon bottom electrode 31 of a hollow cylindrical shape having a HSG structure on the inner sidewall of the capacitor holes 18.
A silicon nitride film 32 covers the surface of the silicon bottom electrodes 31, and a tantalum oxide (Ta2O5) film covers the surface of the silicon nitride film 32 and interlevel dielectric film 17. The silicon nitride film 32 suppresses the surface oxidation of the silicon bottom electrode 31, and both the silicon nitride film 32 and Ta2O5 film configure a capacitor insulation film 34 for the stacked capacitors. A metallic top electrode 35 made of TiN covers the surface of the capacitor insulation film 34. One of the bottom electrodes 31, capacitor insulation film 34 and one of the top electrodes 35 configure a stacked capacitor. The HSG structure formed on the bottom electrodes 31 increases the surface of the bottom electrodes 31 to thereby increase the capacitance of the stacked capacitors. A suitable HSG structure is generally formed by using a heat treatment of the silicon layer in a PH3 atmosphere at a substrate temperature of around 700 degrees C.
It is necessary that the space for the stacked capacitors be reduced in the next-generation semiconductor devices. To meet this request, the stacked capacitor must be reduced in size while maintaining the desired capacitance. In the fabrication step of the conventional semiconductor device 30 as described above, a RTN (Rapid Thermal Nitridation) treatment at a substrate temperature of around 700 degrees C. or above is essential to form the HSG structure, which involves formation of a silicon oxide film on the bottom electrode 31 however. The silicon oxide film thus formed has a lower dielectric constant and significantly increases the thickness of the capacitor insulation film to thereby reduce the capacitance of the stacked capacitor. It is generally difficult to remove this silicon oxide film from the bottom electrode.
Thus, use of a MIM capacitor including a metallic bottom electrode, a capacitor insulation film and a metallic top electrode is studied instead of the MIS capacitor, for preventing formation of the silicon oxide film having a lower dielectric constant.
FIG. 4 shows an example of a semiconductor device including the MIM capacitor. The semiconductor device 40 shown in FIG. 4 is similar to the semiconductor device 30 shown in FIG. 3 except for the structure of the stacked capacitor, and thus description of other elements will be omitted here by denoting similar elements by similar reference numerals. The MIM capacitor includes a metallic bottom electrode 41 made of TiN, for example, having a relatively flat surface, and a top electrode 43 opposing the bottom electrode 41 with an intervention of a capacitor insulation film 42 made of Al2O3.
In the MIM capacitor shown in FIG. 4, the capacitor insulation film 42 has a smaller thickness and a higher dielectric constant compared to the capacitor insulation film 34 of the MIS capacitor wherein a silicon oxide film is formed by the RTN treatment. This structure itself allows the stacked capacitor to have a larger capacitance. However, since the bottom electrode 41 of the MIM capacitor has a flat surface and thus a smaller surface area compared to the silicon bottom electrode 31 having a HSG structure in the MIS capacitor. Thus, a desired large capacitance is also difficult to achieve in the MIM capacitor.
JP-A-2000-357783 describes a MIM capacitor including a bottom electrode having an increased surface area. The bottom electrode described in the publication has a convex and convex surface. It is described in the publication that the bottom electrode is deposited by sputtering of a metal at a substrate temperature of 500 to 600 degrees C., or is formed by sputtering at a substrate temperature of 300 to 400 degrees C. and an additional heat treatment at a substrate temperature of 600 to 700 degrees C.